Intel Deploys New Scaling Convention at 65nm

Semiconductor Insights (SI), the leader in technical and patent analyses of integrated circuits and electronic systems, is pleased to announce today the preliminary results of its analyses of Intel's 65nm logic process. «Traditional transistor scaling technology follows the convention of smaller is better. However, our TEM and SEM analysis of Intel's 65nm Pentium D 920 dual-core processor has revealed an innovative and radical shift in Intel's approach that shifts the focus from scaling physical dimensions towards increasing channel strain and enhancing carrier mobilities,» stated Dr. Don Scansen, Process Technology Manager for SI. «This innovation avoids the leakage and reliability challenges involved with scaling down the gate oxide thickness or with introducing a new class of materials into the dielectric. This is the promise of strain engineering, and it is clear that strain technology is delivering on its promise at Intel.»

SI is conducting detailed structural analyses and core transistor characterization of the Pentium D processor family, with preliminary deliverables available to ship to clients today. In addition to Intel's revised scaling approach, SI's analyses has confirmed a new SRAM layout optimized for density with dimensions slightly relaxed from Intel's published data on their SRAM test chip.

«Understandably, vendors frequently do not disclose all of their innovations, choosing to protect any proprietary advantage as long as possible. The ability to discern technical facts from vendor positioning is the value clients derive from our technical analyses,» stated Dr. Scansen. «Understanding Intel's 65nm logic process will be key to vendors seeking to realize their own 65nm commercial production.» In addition to microstructural analyses of the features outlined above, SI is conducting extensive analysis of the SiGe source / drain for PFET including Ge concentration gradient; an analysis of new silicide processing to enable ultrashallow junctions; and scanning capacitance analysis of ultrashallow junctions.

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