Lattice Semiconductor Launches LatticeSC System Chip FPGA Family11 February 2006
Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced its LatticeSC™ System Chip FPGA family, designedto provide the unsurpassed performance and connectivity essential forhigh-speed applications. Fabricated on Fujitsu's 90nm CMOS processtechnology utilizing 300mm wafers, LatticeSC FPGAs are packed with featuresthat accelerate chip-to-chip, chip-to-memory, high-speed serial, backplaneand network data path connectivity to provide "Extreme Performance." TheLatticeSC devices are being announced by Lattice in conjunction with itssecond-generation low-cost LatticeECP2™ family, also fabricated on thesame 90nm technology. [Please see LatticeECP2 Family press release alsodated today].
Integrated into the LatticeSC devices are high-channel count SERDES blockssupporting 3.4Gbps data rates, PURESPEED™ parallel I/O providing anindustry-leading 2Gbps speed, innovative clock management structures, FPGAlogic operating at 500MHz, dense block RAM and Lattice's unique MaskedArray for Cost Optimization (MACO™) embedded structured ASIC blocks.
"LatticeSC FPGAs deliver the highest performance and most robust featureset of any programmable logic product in the industry. Combined with ournew low cost LatticeECP2 devices, and the non-volatile MachXO™ andLatticeXP™ devices, the LatticeSC family establishes the Lattice FPGAportfolio as the broadest and deepest in the market," said Stan Kopec,Lattice corporate vice president of marketing. "LatticeSC devices arearchitected with high performance protocol-based connectivity in mind,"Kopec added. "The LatticeSC FPGA supports an immense breadth of protocols,including PCI Express, Serial RapidIO, Ethernet, Fibre Channel, SONET/SDHand SPI4.2, as well as all the high performance memory standards, includingDDR2, QDR2 and RLDRAM. This level of innovation, integration, standardssupport and speed in an FPGA is unprecedented," Kopec concluded.
LatticeSC: High Channel Count SERDES + flexiPCS™
Lattice FPSCs (Field Programmable System Chips) were the first programmablelogic devices to combine SERDES and embedded Physical Coding Sublayer (PCS)blocks on an FPGA device. LatticeSC devices advance that pioneeringconcept by providing up to 32 SERDES channels, each running at data ratesfrom 600Mbps to 3.4Gbps. To support backplane applications in which thedrive lengths approach 60 inches, designers can enable the TransmitPre-emphasis and Receive Equalization features that are built into theSERDES. The LatticeSC SERDES also has an extremely low typical powerconsumption of 100 mW/channel @ 3.125 Gbps. Jitter specifications at3.2Gbps are 0.29 UI for total transmit jitter and 0.8 UI for total receivejitter tolerance. Other programmable features such as AC/DC coupling andhalf rate modes are also present to provide users with extraordinaryflexibility in implementing their designs.
The flexiPCS block can be configured to support an array of popular dataprotocols, including PCI-Express, 1.02 or 2.04 Gbps Fibre Channel, GigabitEthernet (1000 BaseX), 10 Gigabit Ethernet (XAUI), Serial RapidIO, andSONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support at 10Gbps orabove). The flexiPCS block features best-in-class Ethernet and PCI Expresssupport, with embedded physical layer functionality for encoding/decoding,scrambling/descrambling, clock tolerance compensation, CRCgeneration/checking and multi-channel alignment.
Lattice Innovation: Masked Array for Cost Optimization (MACO)
Although they lack the flexibility of FPGAs, structured ASICs have becomemore popular due to their density and performance. Unlikefull-custom or standard cell ASICs, structured ASIC designs cost far lessbecause they employ only a few masks for customization. Lattice embeds upto 12 structured ASIC blocks, called MACO blocks, within each LatticeSCFPGA. Each MACO block has approximately 50,000 usable ASIC gates that canbe used to implement Intellectual Property (IP) cores requiring maximumperformance together with minimum silicon area and low power dissipation.The MACO blocks also provide abundant routing connections to I/O pins,block RAM and programmable logic blocks.
Lattice plans to introduce a number of LatticeSC devices with pre-designedblocks covering a broad range of common applications that requirehigh-speed connectivity. Pre-designed MACO-based IP will include Lattice'sinnovative flexiMAC™ multiprotocol communications engine supportingmulti-layered protocols such as PCI Express and Ethernet, as well as SPI4.2and high speed DRAM/SRAM Memory Controllers. Lattice will offer thesestandard MACO IP functions pre-programmed into special versions of itsLatticeSC family, which is designated the M-series.
LatticeSC PURESPEED I/O: 2Gbps Extreme Performance and Connectivity
LatticeSC PURESPEED I/Os support a broad range of differential andsingle-ended I/O standards, including LVTTL, LVCMOS, SSTL, HSTL, GTL+,LVDS, LVPECL and Hypertransport. Each LatticeSC I/O pin includes an InputDelay (INDEL) alignment block with 144 taps at 40ps intervals. Forhigh-speed source synchronous I/O, PURESPEED I/O technology features anAdaptive Input Logic (AIL) block for closed-loop pin timing monitoring andcontrol. This feature dynamically maintains proper setup and hold timemargins on a bit-by-bit basis. Using this feature, designs can accuratelysupport speeds of up to 2Gbps on a single pin.
LatticeSC FPGAs also provide dedicated gearbox logic for SDR, DDR1 and DDR2interfaces. On-chip clock dividers support the clocking requirements ofthe gearbox logic, reducing the need to use generic PLL/DLL resources forthis purpose.
Low power On Die Termination (ODT) is provided to minimize stub lengths,which improves performance. Dynamic switching of the termination ishandled automatically on the device to support standards such as DDR2memory.
FPGA Fabric and Embedded Block RAM
The LatticeSC device is manufactured on Fujitsu's 90nm CMOS processtechnology which, combined with an optimized logic block and ample routing,yields an FPGA fabric easily capable of 500MHz performance (e.g., 64-bitaddress decode). The basic logic element of the array is the ProgrammableFunction Unit (PFU), which can be configured for logic, arithmetic anddistributed RAM/ROM functions. PFUs are divided into four slices, eachcontaining two 4-input SRAM Look-up Tables (LUTs) plus registers. Slicesare individually configurable and can be cascaded, as can the PFUs forlarger functions. Densities in the family span 15K to 115K LUTs.
LatticeSC devices offer 1 to 7.8 Mbit embedded block RAM (EBR) capable of500HMz operation. Each 18Kb sysMEM EBR block can implement single port,true dual port and pseudo-dual port or FIFO memories. Dedicated FIFOsupport logic allows the LatticeSC devices to efficiently implement FIFOswithout consuming LUTs or routing resources for flag generation.
The Lattice SC FPGA is also packed with hierarchical clocking resourcesand, unlike competitive devices, provides both PLL and DLL resources todeliver a no-compromise solution for clock management.
1V Core Supply for Low Power Applications
The LatticeSC FPGA fabric features an industry-exclusive expanded operatingrange power supply core, supporting core Vcc power supplies of both 1.2Vand 1V. Customers with very tight power budgets can use a 1V power supplyto reduce core FPGA power dissipation by over 50%, while decreasing fabricperformance by only 15%.
FreedomChip Cost Reduction
For high volume applications, Lattice also announced plans for acost-reduction path for its LatticeSC family. Customers can reduce theprice of selected LatticeSC FPGA designs by up to 50% by converting to thepin compatible Lattice FreedomChip™. Through automatic insertion ofscan logic, the customer's netlist is utilized to produce low costcustom-tested silicon without the need for difficult back-end designconversion associated with traditional structured ASICs. Further detailson Lattice's FreedomChip technology will be announced during the first halfof 2006.
Sample Application for the LatticeSC FPGA
A typical application for the LatticeSC FPGA is a universalconnectivity bridge in a multi-service networking system. A singleLatticeSC device can support the various data streams used in today'snetworks. To handle traffic shaping, the LatticeSC device will seamlesslyinterface multiple 10G network processors using multiple SPI4.2 coresembedded in structured ASIC blocks. High-speed memory interfaces arerequired to buffer these faster line rates and the LatticeSC supports allof the latest memory standards. To interface to a terabit switch fabric,the LatticeSC FPGA can drive a system backplane with up to 32 SERDESchannels supporting a number of serial standards such as Serial RapidIO,SONET/SDH, PCI Express, Ethernet and Fibre Channel.
Design Tools and IP Support
Design support for LatticeSC devices is provided by the Lattice ispLEVER®Version 5.1 Service Pack 2 design tool suite. The ispLEVER tools providedesigners with access, in one software package, to all Lattice digitaldevices and include simulation and synthesis support from Mentor Graphicsand Synplicity.
An extensive range of IP cores, particularly suited for high-volumeapplications, will be available from both Lattice and its IP partners.Complete details of IP support will be announced throughout 2006.
Availability and Pricing
Prototypes of the first LatticeSC device, the LFSC25, are availablenow. Remaining devices in the family will be moved to production during2006. The LFSC25 has 8 or 16 SERDES channels, depending on the packageoption, running at 600Mbps to 3.4Gbps. The FPGA fabric offers 25,000 PFUs,1.92Mbit embedded block RAM, and 6 MACO structured ASIC blocks. The LFSC25will be offered in a 900-ball fine pitch BGA (fpBGA) and 1020-ball flipchip BGA.
Projected pricing for the basic LFSC25 in the 900fpBGA package inquantities of 25,000 for shipment in 2007 is $49.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range ofField Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD),including Field Programmable System Chips (FPSC), Complex ProgrammableLogic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC®) andProgrammable Digital Interconnect Devices (ispGDX®). Lattice also offersindustry leading SERDES products.
Lattice is "Bringing the Best Together" with comprehensive solutions forsystem design, including an unequaled portfolio of non-volatileprogrammable devices that deliver instant-on operation, security and"single chip solution" space savings.
Lattice products are sold worldwide through an extensive network ofindependent sales representatives and distributors, primarily to OEMcustomers in communications, computing, industrial, consumer, automotive,medical and military end markets. Company headquarters are located at 5555NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000,fax 503-268-8037. For more information about Lattice SemiconductorCorporation, visit http://www.latticesemi.com
This release contains forward-looking statements that involve estimates,assumptions, risks and uncertainties. Many factors could cause actualresults to differ materially from those expressed in such statements. Withregard to statements herein concerning the timing of the introduction ofnew products, product features and product support, the release of suchproducts will depend on a number of technical factors including timely andefficient completion of product design and software, timely and efficientimplementation of wafer manufacturing and assembly processes for our new
products and effective cooperation with our wafer suppliers and assemblycontractors. With regard to statements herein concerning product pricing,the semiconductor industry is characterized by intense competition. Thepricing of Lattice's products depends on a number of factors, includingactions taken by our competitors, market acceptance of, and demand for, ourproducts, product performance and manufacturing yields. In addition to theforegoing, other key factors that could cause our actual results to differmaterially from the forward-looking statements herein are detailed in theCompany's periodic reports filed with the Securities and ExchangeCommission. Actual results may differ materially from forward-lookingstatements.
Lattice Semiconductor Corporation, Lattice (& design), L (& design),flexiMAC, flexiPCS, FreedomChip, LatticeECP2, LatticeXP, MachXO, MACO,LatticeSC, ispGDX, ispLEVER, ispPAC, PURESPEED and specific productdesignations are either registered trademarks or trademarks of LatticeSemiconductor Corporation or its subsidiaries in the United States and/orother countries.
GENERAL NOTICE: Other product names used in this publication are foridentification purposes only and may be trademarks of their respectiveholders.
EDITORIAL/READER CONTACT:Brian KiernanCorporate Communications ManagerLattice Semiconductor Corporation503-268-8739 voice503-268-8193 faxbrian.kiernan@latticesemi.com
SOURCE: Lattice Semiconductor Corporation
Source: marketwire
All trademarks and copyrighted information contained herein are the property of their respective owners.
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