TSMC Validates 90nm Process Technology with Mentor Graphics Calibre xRC Test Chip13 January 2005
Mentor Graphics Corporation (Nasdaq:MENT - News) today announced that TSMC used a comparison of Calibre xRC results, field solver data and silicon measurements as part of the validation for its 90nm process technology.
"The objective of the TSMC 90nm test chip program was to validate the stability of extraction correlation of the 90nm process using third-party vendor extraction tools such as Mentor Graphics® Calibre xRC," said Edward Wan, senior director of design service product marketing at TSMC. "As a result, our mutual customers can design to our leading-edge Nexsys technology with confidence in the accuracy of parasitic extraction results."
The TSMC 90nm test chip program showed that the Calibre xRC results matched measured silicon as well as industry-standard numerical tools for parasitic resistance, inductance and capacitance (R, L and C). TSMC and Mentor Graphics worked collaboratively on the test structures and the measurement technique to accurately quantify and measure 90nm parasitic effects. The test structures that were developed comprised a wide range of line widths and pattern densities to evaluate the effects of process variation across the wafer and across a single die.
"Customers can have confidence that Calibre xRC parasitic extraction will match silicon results," said Joe Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "At the 90nm technology process node, designers not only require that new nanometer effects be captured, but they also demand higher accuracy. The test chip results proved the robust nature of the TSMC 90nm process and the accuracy of Calibre xRC."
The Calibre xRC tool can also support key 90nm process capabilities including selective process biasing, length of diffusion (LOD), source / drain and polysilicon gate resistance and metal fill. In modeling such advanced silicon processes the Calibre xRC tool extracts highly accurate RLC parasitics to enable a complete array of analysis requirements.
Design Kit Support
Calibre LVS, Calibre DRC and Calibre xRC rule files for TSMC's latest process technologies can be found on the TSMC customer Web site at http://online.tsmc.com/online/login.jsp. The Calibre rule files are fully compatible with TSMC process design kits for AMS, RF and digital design process technologies, and support all commonly used design creation environments.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT - News) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 3,800 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070- 7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and Calibre are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
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Contact:
Mentor Graphics
Carole Thurman, 503-685-4716
carole_thurman@mentor.com
or
Sonia Harrison, 503-685-1165
sonia_harrison@mentor.com
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Source: Mentor Graphics
Source: Business Wire via Yahoo
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